Demand for a nonvolatile semiconductor memory device that is small and has a large capacity has been increasing rapidly, and a NAND type flash memory, in which high integration and large capacitivity can be expected, has been paid attention.
It will be necessary that a design rule should be reduced to proceeded high integration and large capacity. For reducing the design rules, further micro processing of wiring patterns will be required.
For realizing further micro processing such as wiring patterns, a very high quality of processing technique is required; therefore, reduction of the design rules has become difficult.
Thus, in late years, large number of inventions on semiconductor memory devices, in which a three-dimensional memory cell has been suggested to raise integration degree of the memory (Japanese Patent Laid-Open No. 2003-078044, U.S. Pat. No. 5,599,724, U.S. Pat. No. 5,707,885, “Masuoka et al. “Novel Ultrahigh-Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEEE TRANSACTION SON ELECTRON DEVICES, VOL. 50, NO. 4, pp 945-951, April 2003”.
Many of the conventional semiconductor memory device, in which a three dimensional memory cell is placed, need to proceed Photo Etching Process (hereinafter called “PEP”, which represents so-called a process to proceed a patterning, using photo resist and manufacturing process such as a lithography process and etching, etc.) Here, a Photo Etching Process performed with a smallest line width of the design rule is set as “a critical PEP”, and a Photo Etching Process performed with a line width larger than the smallest line width of the design rule is set as “a rough PEP”. In the conventional semiconductor memory device, in which a three-dimensional memory cell is disposed, it is required that the critical PEP number per one layer of a memory cell part should be equal to or more than 3. Additionally in a conventional semiconductor memory device, there are many of those, in which memory cells are simply stacked, and thus cost increase caused by three-dimensional manufacturing will not be avoided.
In addition, in one of the conventional semiconductor memory devices which placed a three-dimensional memory cell, there is a semiconductor memory device in use of a transistor of a SGT (a column shape) structure (Japanese Patent Laid-Open No. 2003-078044, U.S. Pat. No. 5,599,724, U.S. Pat. No. 5,707,885).
In a semiconductor memory device in use of a transistor of a SGT (a column shape) structure, a process, in which poly-silicon that will become gate electrodes in its side walls are formed after having formed a channel (a body) part of a stacked memory transistor part in the shape of a pillar, is adopted. It is highly possible that problems such as a shortstop between the adjacent gates occur with micro processing, because the structure from the overhead view is the structure like skewering dumplings.
Even more particularly, as disclosed by IEEE TRANSACTION SON ELECTRON DEVICES, VOL. 50, NO 4, pp 945-951, April 2003, after having formed upper pillar and a side wall gate, a lower layer pillar is formed regarding the upper pillar and the sidewall gate as a mask, and thus a lower layer gate is formed. Therefore, as the lower the layer is going, pillar diameter is different. Accordingly, not only a variation of a transistor property occurs in every layer, but also a cell area from the overhead view becomes large, because a pitch at the time of two dimensional placements with a pillar diameter of the bottom layer is fixed. In addition, a pair of adjacent pillars that is disposed in a two dimensional state are separated thoroughly, and an extra process that connects word lines of every layer will be needed. Therefore, the process will become cumbersome.
As for the nonvolatile semiconductor memory device of conventional stacked type, a number of the word line driver that is necessary has increased because there are word lines that exist at least independently in every layer thus; a tip area has grown large.